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ADC1115S125
Single 11-bit ADC; 125 Msps with input buffer; CMOS or LVDS DDR digital outputs
Rev. 01 -- 12 April 2010 Preliminary data sheet
1. General description
The ADC1115S125 is a single channel 11-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power consumption at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1115S125 is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode, thanks to a separate digital output supply. The ADC1115S125 supports the Low Voltage Differential Signalling (LVDS) Double Data Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the user to easily configure the ADC. The device also includes a SPI programmable full-scale to allow flexible input voltage range from 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the baseband to input frequencies of 170 MHz or more, the ADC1115S125 is ideal for use in communications, imaging and medical applications - especially in high Intermediate Frequency (IF) applications thanks to the integrated input buffer. The input buffer ensures that the input impedance remains constant and low and the performance consistent over a wide frequency range.
2. Features and benefits
SNR, 66.5 dBFS / SFDR, 86 dBc Sample rate up to 125 Msps 11-bit pipelined ADC core Clock input divider by 2 for less jitter contribution Integrated input buffer Flexible input voltage range: 1 V (p-p) to 2 V (p-p) CMOS or LVDS DDR digital outputs Pin compatible with the ADC1415S series, the ADC1215S series and the ADC1015S series HVQFN40 package Input bandwidth, 600 MHz Power dissipation, 840 mW including analog input buffer SPI Duty cycle stabilizer Fast OuT of Range (OTR) detection INL 1.25 LSB, DNL 0.25 LSB Offset binary, two's complement, gray code Power-down and Sleep modes
NXP Semiconductors
ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
3. Applications
Wireless and wired broadband communications Portable instrumentation Imaging systems Digital predistortion loop, power amplifier linearization Spectral analysis Ultrasound equipment Software defined radio
4. Ordering information
Table 1. Ordering information fs (Msps) Package Name ADC1115S125HN/C1 125 Description Version SOT618-6 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm Type number
5. Block diagram
SDIO/ODS CS SCLK/DFS
ADC1115S
ERROR CORRECTION AND DIGITAL PROCESSING SPI
OTR
INP INPUT BUFFER INM S/H INPUT STAGE ADC CORE 11-BIT PIPELINED OUTPUT DRIVERS
CMOS: D10 to D0 or LVDS/DDR: D10P, D10M to D0P, D0M CMOS: DAV or LVDS/DDR: DAVP DAVM
OUTPUT DRIVERS
CLOCK INPUT STAGE AND DUTY CYCLE CONTROL
SYSTEM REFERENCE AND POWER MANAGEMENT
PWD OE
CLKP CLKM
VREF REFB VCM SENSE REFT
005aaa146
Fig 1.
Block diagram
ADC1115S125_1
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Preliminary data sheet
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NXP Semiconductors
ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
6. Pinning information
6.1 Pinning
36 SCLK/DFS 37 SDIO/ODS
36 SCLK/DFS
37 SDIO/ODS
39 SENSE
34 OGND
33 VDDO
40 VREF
35 OTR
39 SENSE
34 OGND
33 VDDO
40 VREF
35 OTR
38 CS
terminal 1 index area REFB REFT AGND VCM VDDA5V AGND INM INP AGND 1 2 3 4 5 6 7 8 9
31 DAV
32 n.c.
REFB 30 n.c. 29 n.c. 28 n.c. 27 D0 26 D1 25 D2 24 D3 23 D4 22 D5 21 D6 REFT AGND VCM VDDA5V AGND INM INP AGND
1 2 3 4 5 6 7 8 9
38 CS
terminal 1 index area
31 DAV 30 n.c. 29 n.c. 28 LOW_D0_P 27 LOW_D0_M 26 D1_D2_P 25 D1_D2_M 24 D3_D4_P 23 D3_D4_M 22 D5_D6_P 21 D5_D6_M D7_D8_P 20
005aaa148
ADC1115S HVQFN40
ADC1115S HVQFN40
VDDA3V 10 VDDA3V 11 CLKP 12 CLKM 13 DEC 14 OE 15 PWD 16 D9_D10_M 17 D9_D10_P 18 D7_D8_M 19
VDDA3V 10 VDDA3V 11 CLKP 12 CLKM 13 DEC 14 OE 15 PWD 16 D10 17 D9 18 D8 19 D7 20
005aaa147
Transparent top view Transparent top view
Fig 2.
Pin configuration with CMOS digital outputs selected
Fig 3.
Pin configuration with LVDS/DDR digital outputs selected
6.2 Pin description
Table 2. Symbol REFB REFT AGND VCM VDDA5V AGND INM INP AGND VDDA3V VDDA3V CLKP CLKM DEC OE PWD
ADC1115S125_1
Pin description (CMOS digital outputs) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Type [1] O O G O P G I I G P P I I O I I Description bottom reference top reference analog ground common-mode output voltage analog power supply 5 V analog ground complementary analog input analog input analog ground analog power supply 3 V analog power supply 3 V clock input complementary clock input regulator decoupling node output enable, active LOW power down, active HIGH
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ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Pin description (CMOS digital outputs) Pin 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Type [1] O O O O O O O O O O O O P G O I I/O I I I/O Description data output bit 10 (MSB) data output bit 9 data output bit 8 data output bit 7 data output bit 6 data output bit 5 data output bit 4 data output bit 3 data output bit 2 data output bit 1 data output bit 0 (LSB) not connected not connected not connected data valid output clock not connected output power supply output ground out of range SPI clock / data format select SPI data IO / output data standard SPI chip select reference programming pin voltage reference input/output
Table 2. Symbol D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 n.c. n.c. n.c. DAV n.c. VDDO OGND OTR SCLK/DFS SDIO/ODS CS SENSE VREF
[1]
P: power supply; G: ground; I: input; O: output; I/O: input/output.
Table 3. Symbol D9_D10_M D9_D10_P D7_D8_M D7_D8_P D5_D6_M D5_D6_P D3_D4_M D3_D4_P D1_D2_M D1_D2_P
Pin description (LVDS/DDR) digital outputs) Pin [1] 17 18 19 20 21 22 23 24 25 26 27 28 29 Type [2] O O O O O O O O O O O O Description differential output data D9 and D10 multiplexed, complement differential output data D9 and D10 multiplexed, true differential output data D7 and D8 multiplexed, complement differential output data D7 and D8 multiplexed, true differential output data D5 and D6 multiplexed, complement differential output data D5 and D6 multiplexed, true differential output data D3 and D4 multiplexed, complement differential output data D3 and D4 multiplexed, true differential output data D1 and D2 multiplexed, complement differential output data D1 and D2 multiplexed, true differential output data D0 multiplexed, complement differential output data D0 multiplexed, true not connected
LOW_D0_M LOW_D0_P n.c.
ADC1115S125_1
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ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Pin description ...continued (LVDS/DDR) digital outputs) Pin [1] 30 31 32 Type [2] O O Description not connected data valid output clock, complement data valid output clock, true
Table 3. Symbol n.c. DAVM DAVP
[1] [2]
Pins 1 to 16 and pins 33 to 40 are the same for both CMOS and LVDS DDR outputs (see Table 2) P: power supply; G: ground; I: input; O: output; I/O: input/output.
7. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VO Parameter output voltage Conditions pins D10 to D0 or pins D10P to D0P and pins D10M to D0M on pin VDDA3V on pin VDDA5V VDDA(3V) - VDDO Min -0.4 Max +3.9 Unit V
VDDA(3V) VDDA(5V) VDDO VCC Tstg Tamb Tj
analog supply voltage 3 V analog supply voltage 5 V output supply voltage supply voltage difference storage temperature ambient temperature junction temperature
-0.5 -0.5 -0.5 -55 -40 -
+4.6 +6.0 +4.6 +125 +85 125
V V V V C C C
8. Thermal characteristics
Table 5. Symbol Rth(j-a) Rth(j-c)
[1]
Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to case Conditions
[1] [1]
Typ 30.5 13.3
Unit K/W K/W
Value for six layers board in still air with a minimum of 25 thermal vias.
9. Static characteristics
Table 6. Symbol Supplies VDDA(5V) VDDA(3V) VDDO IDDA(5V) analog supply voltage 5 V analog supply voltage 3 V output supply voltage analog supply current 5 V CMOS mode LVDS DDR mode fclk = 125 Msps; fi =70 MHz 4.75 2.85 1.65 2.85 5.0 3.0 1.8 3.0 46 5.25 3.4 3.6 3.6 V V V V mA Static characteristics[1] Parameter Conditions Min Typ Max Unit
ADC1115S125_1
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ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Table 6. Symbol IDDA(3V) IDDO
Static characteristics[1] ...continued Parameter analog supply current 3 V output supply current Conditions fclk = 125 Msps; fi =70 MHz CMOS mode; fclk = 125 Msps; fi =70 MHz LVDS DDR mode: fclk = 125 Msps; fi =70 MHz Min Typ 205 11 Max Unit mA mA
-
39
-
mA
P
power dissipation
analog supply only Power-down mode Standby mode
-
840 2 40
-
mW mW mW
Clock inputs: pins CLKP and CLKM LVPECL Vi(clk)dif LVDS Vi(clk)dif SINE wave Vi(clk)dif LVCMOS VIL VIH VIL VIH IIL IIH VIL VIH IIL IIH CI LOW-level input voltage HIGH-level input voltage LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current input capacitance 0.7VDDA(3V) 0 2 -10 0 0.7VDDA(3V) -10 -50 4 0.3VDDA(3V) 0.8 VDDA(3V) +10 0.3VDDA(3V) VDDA(3V) +10 +50 V V V V A A V V A A pF differential clock input voltage peak-to-peak 0.8 3.0 V differential clock input voltage peak-to-peak 0.70 V differential clock input voltage peak-to-peak 1.6 V
Logic inputs: pins PWD and OE
Serial peripheral interface: pins CS, SDIO/ODS, SCLK/DFS
Digital outputs, CMOS mode: pins D10 to D0, OTR, DAV Output levels, VDDO = 3 V VOL VOH IOL IOH CO LOW-level output voltage HIGH-level output voltage LOW-level output current HIGH-level output current output capacitance IOL = IOH = 3-state; output level = 0 V 3-state; output level = VDDA(3V) high impedance; OE = HIGH OGND 0.8VDDO 3 0.2VDDO VDDO V V A A pF
Output levels, VDDO = 1.8 V
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ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Table 6. Symbol VOL VOH
Static characteristics[1] ...continued Parameter LOW-level output voltage HIGH-level output voltage Conditions IOL = IOH = Min OGND 0.8VDDO Typ Max 0.2VDDO VDDO Unit V V
Digital outputs, LVDS mode: pins D10P to D0P, D10M to D0M, DAVP and DAVM Output levels, VDDO = 3 V only, Rload = 100 VO(offset) VO(dif) CO II RI CI VI(cm) Bi VI(dif) VO(cm) IO(cm) VVREF Accuracy INL DNL Eoffset EG Supply PSRR power supply rejection ratio 100 mV (p-p) on VDDA(3V) 35 dBc integral non-linearity differential non-linearity offset error gain error guaranteed no missing codes 2 0.5 LSB LSB mV %FS output offset voltage differential output voltage output capacitance input current input resistance input capacitance common-mode input voltage input bandwidth differential input voltage common-mode output voltage common-mode output current voltage on pin VREF output input peak-to-peak VINP = VINM output buffer current set to 3.5 mA output buffer current set to 3.5 mA -5 0.9 1 0.5 0.5VDDA(3V) 0.5 to 1 1.2 350 550 1.3 1.5 600 +5 2 2 1 V mV pF A pF V MHz V V A V V
Analog inputs: pins INP and INM
Common mode output voltage: pin VCM
I/O reference voltage: pin VREF
[1]
Typical values measured at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V; Tamb = 25 C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = -40 C to +85 C at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V, VINP - VINM = -1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified.
ADC1115S125_1
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NXP Semiconductors
ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
10. Dynamic characteristics
10.1 Dynamic characteristics
Table 7. Symbol Dynamic characteristics[1] Parameter Conditions Min Analog signal processing 2H second harmonic level fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz 3H third harmonic level fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz THD total harmonic distortion fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz ENOB effective number of bits fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz SNR signal-to-noise ratio fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz SFDR spurious-free dynamic range fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz IMD Intermodulation distortion fi = 3 MHz fi = 30 MHz fi = 70 MHz fi = 170 MHz
[1]
ADC1115S125 Typ 88 87 85 83 87 86 84 82 86 85 83 81 10.7 10.7 10.7 10.6 66.2 66.2 66.0 65.8 87 86 84 82 89 88 86 84 Max
Unit
-
dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bits bits bits bits dBFS dBFS dBFS dBFS dBc dBc dBc dBc dBc dBc dBc dBc
Typical values measured at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V; Tamb = 25 C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = -40 C to +85 C at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V, VINP - VINM = -1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified.
ADC1115S125_1
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ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
10.2 Clock and digital output timing
Table 8. Symbol Clock and digital output timing characteristics[1] Parameter Conditions Min Clock timing input: pins CLKP and CLKM fclk tlat(data) clk td(s) twake tPD tsu th tr tf tPD tsu th tr tf clock frequency data latency time clock duty cycle sampling delay time wake-up time propagation delay set-up time hold time rise fall time[2] DATA DAV time[2] DATA DATA DAV set-up time hold time rise time[3] DATA DAV fall time[3] DATA DAV
[1]
ADC1115S125 Typ 14 50 50 0.8 tbd 3.9 4.2 4.3 3.5 3.9 4.2 1.4 2.0 100 100 100 100 Max 125 70 55 2.4 2.4 2.4 200 200 200 200
Unit
100 DCS_EN = 1 DCS_EN = 0 30 45 DATA DAV 0.5 0.5 0.5 50 50 50 50
MHz clock cycles % % ns ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps
CMOS mode timing output: pins D10 to D0 and DAV
LVDS DDR mode timing output: pins D10P to D0P, D10M to D0M, DAVP and DAVM propagation delay
Typical values measured at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V; Tamb = 25 C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = -40 C to +85 C at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V, VINP - VINM = -1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified. Measured between 20 % to 80 % of VDDO. Rise time measured from -50 mV to +50 mV; fall time measured from +50 mV to -50 mV.
[2] [3]
ADC1115S125_1
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ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
N
N+1
td(s) N+2 tclk CLKP CLKM tPD (N - 14) (N - 13) (N - 12) (N - 11)
DATA tPD
tsu DAV
th
tclk
005aaa060
Fig 4.
CMOS mode timing
N
N+1
td(s) N+2 tclk CLKP CLKM tPD Dx_Dx + 1_P Dx Dx_Dx + 1_M tsu th tsu th DAVP DAVM tclk
005aaa061
(N - 14)
(N - 13)
(N - 12)
(N - 11)
Dx + 1
Dx
Dx + 1
Dx
Dx + 1
Dx
Dx + 1
Dx
Dx + 1
tPD
Fig 5.
LDVS DDR mode timing
ADC1115S125_1
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ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
10.3 SPI timings
Table 9. Symbol tw(SCLK) tw(SCLKH) tw(SCLKL) tsu th fclk(max)
[1]
Characteristics Parameter SCLK pulse width SCLK pulse width HIGH SCLK pulse width LOW set-up time hold time maximum clock frequency data to SCLKH CS to SCLKH data to SCLKH CS to SCLKH Conditions Min 40 16 16 5 5 2 2 Typ Max 25 Unit ns ns ns ns ns ns ns MHz
SPI timings
Typical values measured at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V; Tamb = 25 C and CL = 5 pF; minimum and maximum values are across the full temperature range Tamb = -40 C to +85 C at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V, VINP - VINM = -1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified
tsu CS
tsu th
tw(SCLKL) tw(SCLK) tw(SCLKH)
th
SCLK
SDIO
R/W
W1
W0
A12
A11
D2
D1
D0
005aaa065
Fig 6.
SPI timing
11. Application information
11.1 Device control
The ADC1115S125 can be controlled via the Serial Peripheral Interface (SPI control mode) or directly via the I/O pins (Pin control mode).
11.1.1 SPI and Pin control modes
The device enters Pin control mode at power-up, and remains in this mode as long as pin CS is held HIGH. In Pin control mode, the SPI pins SDIO, CS and SCLK are used as static control pins. SPI control mode is enabled by forcing pin CS LOW. Once SPI control mode has been enabled, the device will remain in this mode. The transition from Pin control mode to SPI control mode is illustrated in Figure 7.
ADC1115S125_1
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Preliminary data sheet
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ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
CS
Pin control mode Data format offset binary
SPI control mode
SCLK/DFS
Data format two's complement LVDS DDR
SDIO/ODS
CMOS
R/W
W1
W0
A12
005aaa039
Fig 7.
Control mode selection
When the device enters SPI control mode, the output data standard and data format are determined by the level on pin SDIO as soon as a transition is triggered by a falling edge on CS.
11.1.2 Operating mode selection
The active ADC1115S125 operating mode (Power-up, Power-down or Sleep) can be selected via the SPI interface (see Table 19) or using pins PWD and OE in Pin control mode, as described in Table 10.
Table 10. Pin PWD 0 0 1 1 Operating mode selection via pin PWD and OE Pin OE 0 1 0 1 Operating mode Power-up Power-up Sleep Power-down Output high-Z no yes yes yes
11.1.3 Selecting the output data standard
The output data standard (CMOS or LVDS DDR) can be selected via the SPI interface (see Table 23) or using pin ODS in Pin control mode. LVDS DDR is selected when ODS is HIGH, otherwise CMOS is selected.
11.1.4 Selecting the output data format
The output data format can be selected via the SPI interface (offset binary, two's complement or gray code; see Table 23) or using pin DFS in Pin control mode (offset binary or two's complement). Offset binary is selected when DFS is LOW. When DFS is HIGH, two's complement is selected.
11.2 Analog inputs
11.2.1 Input stage
The analog input of the ADC1115S125 supports differential or single-ended input drive. Optimal performance is achieved using differential inputs. The ADC inputs are internally biased and need to be decoupled. The full scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p) via a programmable internal reference (see Section 11.3 and Table 21 further details).
ADC1115S125_1
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ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
The equivalent circuit of the input buffer followed by the Sample and Hold (S/H) input stage, including ElectroStatic Discharge (ESD) protection and circuit and package parasitics, is shown in Figure 8.
package
ESD
parasitics
switch INP 8
Ron = 15 4 pF
internal clock INPUT BUFFER
Ron = 15
sampling capacitor
switch
INM
7
4 pF
internal clock
sampling capacitor
005aaa107
Fig 8.
Input sampling circuit and input buffer
The integrated input buffer offers the following advantages:
* The kickback effect is avoided - the charge injection and glitches generated by the
S/H input stage are isolated from the input circuitry. So there's no need for additional filtering.
* The input capacitance is very low and constant over a wide frequency range, which
makes the ADC1115S125 easy to drive. The sample phase occurs when the internal clock (derived from the clock signal on pin CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the clock signal goes LOW, the stage enters the hold phase and the voltage information is transmitted to the ADC core.
ADC1115S125_1
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NXP Semiconductors
ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
11.2.2 Transformer
The configuration of the transformer circuit is determined by the input frequency. The configuration shown in Figure 9 would be suitable for a baseband application.
ADT1-1WT Analog input
100 nF 100 nF
INP
50 100 nF 100 nF
INM VCM
100 nF
100 nF
005aaa108
Fig 9.
Single transformer configuration suitable for baseband applications
The configuration shown in Figure 10 is recommended for high frequency applications. In both cases, the choice of transformer will be a compromise between cost and performance.
ADT1-1WT
100 nF 50
ADT1-1WT
100 nF
INP
Analog input
100 50 100 nF
INM VCM
100 nF
100 nF
100 nF
005aaa109
Fig 10. Dual transformer configuration suitable for high intermediate frequency application
ADC1115S125_1
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ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
11.3 System reference and power management
11.3.1 Internal/external references
The ADC1115S125 has a stable and accurate built-in internal reference voltage to adjust the ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF and SENSE (programmable in 1 dB steps between 0 dB and -6 dB via control bits INTREF[2:0] when bit INTREF_EN = 1; see Table 21). See Figure 12, Figure 13, Figure 14 and Figure 15. The equivalent reference circuit is shown in Figure 11. External reference is also possible by providing a voltage on pin VREF as described in Figure 14.
REFT REFERENCE AMP REFB
VREF EXT_ref BANDGAP REFERENCE
BUFFER
EXT_ref
ADC CORE SENSE SELECTION LOGIC
005aaa164
Fig 11. Reference equivalent schematic
If bit INTREF_EN is set to 0, the reference voltage will be determined either internally or externally as detailed in Table 11.
Table 11. Selection internal (Figure 12) internal (Figure 13) external (Figure 14) internal via SPI (Figure 15)
[1]
ADC1115S125_1
Reference selection SPI bit INTREF_EN 0 0 0 1 SENSE pin AGND VREF pin 330 pF capacitor to AGND full scale (p-p) 2V 1V 1 V to 2 V 1 V to 2 V
pin VREF connected to pin SENSE and via a 330 pF capacitor to AGND VDDA(3V) external voltage between 0.5 V and 1 V[1]
pin VREF connected to pin SENSE and via 330 pF capacitor to AGND
The voltage on pin VREF is doubled internally to generate the internal reference voltage.
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ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Figure 12 to Figure 15 illustrate how to connect the SENSE and VREF pins to select the required reference voltage source.
VREF
330 pF
VREF
330 pF
REFERENCE EQUIVALENT SCHEMATIC
REFERENCE EQUIVALENT SCHEMATIC SENSE
SENSE
005aaa116
005aaa117
Fig 12. Internal reference, 2 V (p-p) full scale
Fig 13. Internal reference, 1 V (p-p) full scale
VREF
0.1 F
VREF
V
REFERENCE EQUIVALENT SCHEMATIC
330 pF
REFERENCE EQUIVALENT SCHEMATIC SENSE
SENSE
VDDA
005aaa119
005aaa118
Fig 14. External reference, 1 V (p-p) to 2 V (p-p) full-scale
Fig 15. Internal reference via SPI, 1 V (p-p) to 2 V (p-p) full-scale
11.3.2 Reference gain control
The reference gain is programmable between 0 dB to -6 dB in 1 dB steps via the SPI (see Table 21). The corresponding full-scale input voltage range varies between 2 V (p-p) and 1 V (p-p), as shown in Table 12:
Table 12. INTREF 000 001 010 011 100 101 110 111 Reference SPI gain control Gain 0 dB -1 dB -2 dB -3 dB -4 dB -5 dB -6 dB reserved full scale (p-p) 2V 1.78 V 1.59 V 1.42 V 1.26 V 1.12 V 1V x
11.3.3 Common-mode output voltage (VO(cm))
A 0.1 F filter capacitor should be connected between pin VCM and ground.
11.3.4 Biasing
The common-mode input voltage (VI(cm)) on pins INP and INM is set internally. The input buffer bias current can be set to one of three levels (high, medium or low) via the SPI (see Table 22).
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ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
11.4 Clock input
11.4.1 Drive modes
The ADC1115S125 can be driven differentially (SINE, LVPECL or LVDS) with little or no degradation on dynamic performances. It can also be driven by a single-ended LVCMOS signal connected to pin CLKP (CLKM should be connected to ground via a capacitor) or CLKM (CLKP should be connected to ground via a capacitor).
LVCMOS clock input
CLKP CLKP CLKM LVCMOS clock input CLKM
005aaa174
005aaa053
a. Rising edge LVCMOS Fig 16. LVCMOS single-ended clock input
b. Falling edge LVCMOS
CLKP Sine clock input
Sine clock input
CLKP
CLKM
CLKM
005aaa173
005aaa054
a. Sine clock input
b. Sine clock input (with transformer)
CLKP LVDS clock input LVPECL clock input CLKM
CLKP
CLKM
005aaa055
005aaa172
c. LVDS clock input Fig 17. Differential clock input
d. LVPECL clock input1
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ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
11.4.2 Equivalent input circuit
The equivalent circuit of the input clock buffer is shown in Figure 18. The common-mode voltage of the differential input stage is set via internal 5 k resistors.
PACKAGE
ESD
PARASITICS
CLKP
Vcm(clk) SE_SEL SE_SEL
5 k
5 k
CLKM
005aaa056
Fig 18. Equivalent input circuit
Single-ended or differential clock inputs can be selected via the SPI interface (see Table 20). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via control bit SE_SEL. If single-ended is implemented without setting SE_SEL to the appropriate value, the unused pin should be connected to ground via a capacitor.
11.4.3 Duty cycle stabilizer
The duty cycle stabilizer can improve the overall performances of the ADC by compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is active (bit DCS_EN = 1; see Table 20), the circuit can handle signals with duty cycles of between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled (DCS_EN = 0), the input clock signal should have a duty cycle of between 45% and 55%.
11.4.4 Clock input divider
The ADC1115S125 contains an input clock divider that divides the incoming clock by a factor of 2 (when bit CLKDIV = 1; see Table 20). This feature allows the user to deliver a higher clock frequency with better jitter performance, leading to a better SNR result once acquisition has been performed.
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ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
11.5 Digital outputs
11.5.1 Digital output buffers: CMOS mode
The digital output buffers can be configured as CMOS by setting bit LVDS/CMOS to 0 (see Table 23). Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS digital output buffer is shown in Figure 19. The buffer is powered by a separate OGND/VDDO to ensure 1.8 V to 3.3 V compatibility and is isolated from the ADC core. Each buffer can be loaded by a maximum of 10 pF.
VDDO PARASITICS ESD PACKAGE
LOGIC DRIVER
50
Dx
OGND
005aaa057
Fig 19. CMOS digital output buffer
The output resistance is 50 and is the combination of the an internal resistor and the equivalent output resistance of the buffer. There is no need for an external damping resistor. The drive strength of both data and DAV buffers can be programmed via the SPI in order to adjust the rise and fall times of the output digital signals (see Table 30):
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ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
11.5.2 Digital output buffers: LVDS DDR mode
The digital output buffers can be configured as LVDS DDR by setting bit LVDS/CMOS to 1 (see Table 23).
VCCO 3.5 mA typ - +
DnP/Dn + 1P 100 DnM/Dn + 1M RECEIVER
+
- OGND
005aaa058
Fig 20. LVDS DDR digital output buffer - externally terminated
Each output should be terminated externally with a 100 resistor (typical) at the receiver side (Figure 20) or internally via SPI control bits LVDS_INT_TER[2:0] (see Figure 21 and Table 32).
VCCO 3.5 mA typ - +
DxP/Dx + 1P RECEIVER DxM/Dx + 1M
100
+
- OGND
005aaa059
Fig 21. LVDS DDR digital output buffer - internally terminated
The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via the SPI (bits DAVI[1:0] and DATAI[1:0]; see Table 31) in order to adjust the output logic voltage levels.
Table 13. 000 001 010 011 100
ADC1115S125_1
LVDS DDR output register 2 Resistor value () no internal termination 300 180 110 150
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LVDS_INT_TER[2:0]
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ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
LVDS DDR output register 2 ...continued Resistor value () 100 81 60
Table 13. 101 110 111
LVDS_INT_TER[2:0]
11.5.3 Data valid (DAV) output clock
A data valid output clock signal (DAV) is provided that can be used to capture the data delivered by the ADC1115S125. Detailed timing diagrams for CMOS and LVDS DDR modes are provided in Figure 4 and Figure 5 respectively.
11.5.4 Out-of-Range (OTR)
An out-of-range signal is provided on pin OTR. The latency of OTR is fourteen clock cycles. The OTR response can be speeded up by enabling Fast OTR (bit FASTOTR = 1; see Table 29). In this mode, the latency of OTR is reduced to only four clock cycles. The Fast OTR detection threshold (below full scale) can be programmed via bits FASTOTR_DET[2:0].
Table 14. 000 001 010 011 100 101 110 111 Fast OTR register Detection level (dB) -20.56 -16.12 -11.02 -7.82 -5.49 -3.66 -2.14 -0.86
FASTOTR_DET[2:0]
11.5.5 Digital offset
By default, the ADC1115S125 delivers output code that corresponds to the analog input. However it is possible to add a digital offset to the output code via the SPI (bits DIG_OFFSET[5:0]; see Table 25).
11.5.6 Test patterns
For test purposes, the ADC1115S125 can be configured to transmit one of a number of predefined test patterns (via bits TESTPAT_SEL[2:0]; see Table 26). A custom test pattern can be defined by the user (TESTPAT_USER; see Table 27 and Table 28) and is selected when TESTPAT_SEL[2:0] = 101. The selected test pattern will be transmitted regardless of the analog input.
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ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
11.5.7 Output codes versus input voltage
Table 15. VINP - VINM < -1 -1.0000000 -0.9990234 -0.9980469 -0.9970703 -0.996093 .... -0.0019531 -0.0009766 0.0000000 +0.0009766 +0.0019531 .... +0.9960938 +0.9970703 +0.9980469 +0.9990234 +1.0000000 > +1 Output codes Offset binary 000 0000 0000 000 0000 0000 000 0000 0001 000 0000 0010 000 0000 0011 000 0000 0100 .... 011 1111 1110 011 1111 1111 100 0000 0000 100 0000 0001 100 0000 0010 .... 111 1111 1011 111 1111 1100 111 1111 1101 111 1111 1110 111 1111 1111 111 1111 1111 Two's complement 100 0000 0000 100 0000 0000 100 0000 0001 100 0000 0010 100 0000 0011 100 0000 0100 .... 111 1111 1110 111 1111 1111 000 0000 0000 000 0000 0001 000 0000 0010 .... 011 1111 1011 011 1111 1100 011 1111 1101 011 1111 1110 011 1111 1111 011 1111 1111 OTR pin 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
11.6 Serial Peripheral Interface (SPI)
11.6.1 Register description
The ADC1115S125 serial interface is a synchronous serial communications port that allows for easy interfacing with many commonly-used microprocessors. It provides access to the registers that control the operation of the chip. This interface is configured as a 3-wire type (SDIO as bidirectional pin) Pin SCLK is the serial clock input and CS is the chip select pin. Each read/write operation is initiated by a LOW level on CS. A minimum of three bytes will be transmitted (two instruction bytes and at least one data byte). The number of data bytes is determined by the value of bits W1 and W2 (see Table 17).
Table 16. Bit Description Instruction bytes for the SPI MSB 7 R/W[1] A7
[1] [2]
LSB 6 W1[2] A6 5 W0[2] A5 4 A12 A4 3 A11 A3 2 A10 A2 1 A9 A1 0 A8 A0
Bit R/W indicates whether it is a read (1) or a write (0) operation. Bits W1 and W0 indicate the number of bytes to be transferred after the instruction byte (see Table 17).
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ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Number of data bytes to be transferred after the instruction bytes W0 0 1 0 1 Number of bytes transmitted 1 byte 2 bytes 3 bytes 4 bytes or more
Table 17. W1 0 0 1 1
Bits A12 to A0 indicate the address of the register being accessed. In the case of a multiple byte transfer, this address is the first register to be accessed. An address counter is increased to access subsequent addresses. The steps involved in a data transfer are as follows: 1. A falling edge on CS in combination with a rising edge on SCLK determine the start of communications. 2. The first phase is the transfer of the 2-byte instruction. 3. The second phase is the transfer of the data which can vary in length but will always be a multiple of 8 bits. The MSB is always sent first (for instruction and data bytes). 4. A rising edge on CS indicates the end on data transmission.
CS
SCLK
SDIO
R/W W1
W0
A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Instruction bytes
Register N (data)
Register N + 1 (data)
005aaa062
Fig 22. SPI mode timing
11.6.2 Default modes at start-up
During circuit initialization, it does not matter which output data standard has been selected. At power-up, the device enters Pin control mode. A falling edge on CS will trigger a transition to SPI control mode. When the ADC1115S125 enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by the level on pin SDIO (see Figure 23). Once in SPI control mode, the output data standard can be changed via bit LVDS/CMOS in Table 23. When the ADC1115S125 enters SPI control mode, the output data format (two's complement or offset binary) is determined by the level on pin SCLK (gray code can only be selected via the SPI). Once in SPI control mode, the output data format can be changed via bit DATA_FORMAT[1:0] in Table 23.
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ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
CS
SCLK (Data format)
SDIO (CMOS LVDS DDR) Offset binary, LVDS DDR default mode at start-up
005aaa063
Fig 23. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR
CS
SCLK (Data format)
SDIO (CMOS LVDS DDR)
two's complement, CMOS default mode at start-up
005aaa064
Fig 24. Default mode at start-up: SCLK HIGH = two's complement; SDIO LOW = CMOS
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11.6.3 Register allocation map
Table 18. Addr. Hex 0005 0006 0008 0010 Register allocation map Register name Reset and operating mode Clock R/W R/W R/W Bit definition Bit 7 SW_RST Bit 6 Bit 5 Bit 4 Bit 3 DIFF_SE INTREF_EN OUTBUF DAVINV DIG_OFFSET[5:0] TESTPAT_USER[10:3] TESTPAT_USER[2:0] DAVI_x2_EN DAVI[1:0] BIT_BYTE_WISE FASTOTR DAV_DRV[1:0] DATAI_x2_EN FASTOTR_DET[2:0] DATA_DRV[1:0] DATAI[1:0] TESTPAT_SEL[2:0] OUTBUS_SWAP Bit 2 Bit 1 Bit 0 OP_MODE[1:0] CLKDIV INTREF[2:0] IB_IBIAS[1:0 ] DCS_EN RESERVED[2:0] SE_SEL LVDS_ CMOS Default Bin 0000 0000 0000 0001 0000 0000 0000 0011 0000 0000 0000 1110 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1110 0000 0000 0000 0000
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Internal reference R/W Input buffer Output data standard. Output clock Offset Test pattern 1 Test pattern 2 Test pattern 3 Fast OTR CMOS output R/W R/W R/W R/W R/W R/W R/W R/W R/W
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
0011 0012 0013 0014 0015 0016 0017 0020 0021 0022
DATA_FORMAT[1:0]
DAVPHASE[2:0]
ADC1115S125
LVDS DDR O/P 1 R/W LVDS DDR O/P 2 R/W
LVDS_INT_TER[2:0]
NXP Semiconductors
ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Table 19. Bit 7
Reset and operating mode control register (address 0005h) bit description Symbol SW_RST Access R/W 0 1 Value Description reset digital section no reset performs a reset on SPI registers reserved not used operating mode 00 01 10 11 normal (Power-up) Power-down Sleep normal (Power-up)
6 to 4 3 to 2 1 to 0
RESERVED[2:0] OP_MODE[1:0] R/W
000 00
Table 20. Bit 7 to 5 4 -
Clock control register (address 0006h) bit description Symbol SE_SEL Access R/W 0 1 Value 000 Description not used single-ended clock input pin select CLKM CLKP differential/single ended clock input select 0 1 fully differential single-ended not used clock input divide by 2 0 1 disabled enabled duty cycle stabilizer 0 1 disabled enabled
3
DIFF_SE
R/W
2 1
CLKDIV R/W
0
0
DCS_EN
R/W
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11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Table 21. Bit 7 to 4 3 -
Internal reference control register (address 0008h) bit description Symbol INTREF_EN Access R/W 0 1 Value 0000 Description not used programmable internal reference enable disable active programmable internal reference 000 001 010 011 100 101 110 111 0 dB (FS = 2 V) -1 dB (FS = 1.78 V) -2 dB (FS = 1.59 V) -3 dB (FS = 1.42 V) -4 dB (FS = 1.26 V) -5 dB (FS = 1.12 V) -6 dB (FS = 1 V) reserved
2 to 0
INTREF[2:0]
R/W
Table 22. Bit 7 to 2 1 to 0 -
Input buffer control register (address 0010h) bit description Symbol IB_IBIAS[1:0] Access R/W 00 01 10 11 Value 000000 Description not used input buffer bias current not used medium low high
Table 23. Bit 7 to 5 4 -
Output data standard control register (address 0011h) bit description Symbol LVDS_CMOS Access R/W 0 1 Value 000 Description not used output data standard: LVDS DDR or CMOS CMOS LVDS DDR output buffers enable 0 1 output enabled output disabled (high Z) output bus swapping 0 1 no swapping output bus is swapped (MSB becomes LSB and vice versa) output data format 00 01 10 11 offset binary two's complement gray code offset binary
3
OUTBUF
R/W
2
OUTBUS_SWAP
R/W
1 to 0
DATA_FORMAT[1:0]
R/W
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11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Table 24. Bit 7 to 4 3 -
Output clock register (address 0012h) bit description Symbol DAVINV Access R/W 0 1 Value 0000 Description not used output clock data valid (DAV) polarity normal inverted DAV phase select 000 001 010 011 100 101 110 111 output clock shifted (ahead) by 3 ns output clock shifted (ahead) by 2.5 ns output clock shifted (ahead) by 2 ns output clock shifted (ahead) by 1.5 ns output clock shifted (ahead) by 1 ns output clock shifted (ahead) by 0.5 ns default value as defined in timing section output clock shifted (delayed) by 0.5 ns
2 to 0
DAVPHASE[2:0]
R/W
Table 25. Bit 7 to 6 5 to 0 -
Offset register (address 0013h) bit description Symbol DIG_OFFSET[5:0] Access R/W 011111 ... 000000 ... 100000 ... 0 ... -32 LSB Value 00 Description not used digital offset adjustment +31 LSB
Table 26. Bit 7 to 3 2 to 0 -
Test pattern register 1 (address 0014h) bit description Symbol TESTPAT_SEL[2:0] Access R/W 000 001 010 011 100 101 110 111 Value 00000 Description not used digital test pattern select off mid scale -FS +FS toggle `1111..1111'/'0000..0000' custom test pattern `1010..1010.' `010..1010'
Table 27. Bit 7 to 0
Test pattern register 2 (address 0015h) bit description Symbol TESTPAT_USER[10:3] Access R/W Value 00000000 Description custom digital test pattern (bits 10 to 3)
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11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Table 28. Bit 7 to 5 4 to 0 Table 29. Bit 7 to 4 3 -
Test pattern register 3 (address 0016h) bit description Symbol TESTPAT_USER[2:0] Access R/W Value 000 00000 Description custom digital test pattern (bits 2 to 0) not used
Fast OTR register (address 0017h) bit description Symbol FASTOTR Access R/W 0 1 Value 0000 Description not used fast Out-of-Range (OTR) detection disabled enabled set fast OTR detect level 000 001 010 011 100 101 110 111 -20.56 dB -16.12 dB -11.02 dB -7.82 dB -5.49 dB -3.66 dB -2.14 dB -0.86 dB
2 to 0
FASTOTR_DET[2:0]
R/W
Table 30. Bit 7 to 4 3 to 2 -
CMOS output register (address 0020h) bit description Symbol DAV_DRV[1:0] Access R/W 00 01 10 11 Value 0000 Description not used drive strength for DAV CMOS output buffer low medium high very high drive strength for DATA CMOS output buffer 00 01 10 11 low medium high very high
1 to 0
DATA_DRV[1:0]
R/W
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11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Table 31. Bit 7 to 6 5 -
LVDS DDR output register 1 (address 0021h) bit description Symbol DAVI_x2_EN Access R/W 0 1 Value 00 Description not used double LVDS current for DAV LVDS buffer disabled enabled LVDS current for DAV LVDS buffer 00 01 10 11 3.5 mA 4.5 mA 1.25 mA 2.5 mA double LVDS current for DATA LVDS buffer 0 1 disabled enabled LVDS current for DATA LVDS buffer 00 01 10 11 3.5 mA 4.5 mA 1.25 mA 2.5 mA
4 to 3
DAVI[1:0]
R/W
2
DATAI_x2_EN
R/W
1 to 0
DATAI[1:0]
R/W
Table 32. Bit 7 to 4 3 -
LVDS DDR output register 2 (address 0022h) bit description Symbol BIT/BYTE_WISE Access R/W 0 1 Value 0000 Description not used DDR mode for LVDS output bit wise (even data bits output on DAV rising edge / odd data bits output on DAV falling edge) byte wise (MSB data bits output on DAV rising edge / LSB data bits output on DAV falling edge) internal termination for LVDS buffer (DAV and DATA) 000 001 010 011 100 101 110 111 no internal termination 300 180 110 150 100 81 60
2 to 0
LVDS_INTTER[2:0]
R/W
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12. Package outline
HVQFN40: plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm
SOT618-6
D
B
A
terminal 1 index area
E
A
A1 c
detail X
e1 1/2 e e 11 L 10 21 e b 20 v w CAB C y1 C C y
Eh 1/2 e
e2
1 terminal 1 index area 40 Dh 31
30
X
0 Dimensions Unit mm A(1) A1 b c 0.2 D(1) 6.1 6.0 5.9 Dh 4.55 4.40 4.25 E(1) 6.1 6.0 5.9 Eh 4.55 4.40 4.25 e 0.5
2.5 scale e1 4.5 e2 4.5 L 0.5 0.4 0.3
5 mm
v 0.1
w
y
y1 0.1
max 1.00 0.05 0.30 nom 0.85 0.02 0.21 min 0.80 0.00 0.18
0.05 0.05
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version SOT618-6 References IEC JEDEC MO-220 JEITA --European projection
sot618-6_po
Issue date 09-02-23 09-03-04
Fig 25. Package outline SOT618-6 (HVQFN40)
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13. Revision history
Table 33. Revision history Release date 20100412 Data sheet status Change Supersedes notice Document ID ADC1115S125_1
Preliminary data sheet -
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14. Legal information
14.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
(c) NXP B.V. 2010. All rights reserved.
14.3 Disclaimers
Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or
ADC1115S125_1
All information provided in this document is subject to legal disclaimers.
Preliminary data sheet
Rev. 01 -- 12 April 2010
33 of 35
NXP Semiconductors
ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications.
Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
ADC1115S125_1
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Preliminary data sheet
Rev. 01 -- 12 April 2010
34 of 35
NXP Semiconductors
ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
16. Contents
1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.3 11 11.1 11.1.1 11.1.2 11.1.3 11.1.4 11.2 11.2.1 11.2.2 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.5 11.5.1 11.5.2 11.5.3 11.5.4 11.5.5 11.5.6 11.5.7 11.6 11.6.1 11.6.2 11.6.3 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal characteristics . . . . . . . . . . . . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Clock and digital output timing . . . . . . . . . . . . . 9 SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Application information. . . . . . . . . . . . . . . . . . 11 Device control . . . . . . . . . . . . . . . . . . . . . . . . . 11 SPI and Pin control modes . . . . . . . . . . . . . . . 11 Operating mode selection. . . . . . . . . . . . . . . . 12 Selecting the output data standard . . . . . . . . . 12 Selecting the output data format. . . . . . . . . . . 12 Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 12 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 14 System reference and power management . . 15 Internal/external references . . . . . . . . . . . . . . 15 Reference gain control . . . . . . . . . . . . . . . . . . 16 Common-mode output voltage (VO(cm)) . . . . . 16 Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . 17 Equivalent input circuit . . . . . . . . . . . . . . . . . . 18 Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 18 Clock input divider . . . . . . . . . . . . . . . . . . . . . 18 Digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . 19 Digital output buffers: CMOS mode . . . . . . . . 19 Digital output buffers: LVDS DDR mode . . . . . 20 Data valid (DAV) output clock . . . . . . . . . . . . . 21 Out-of-Range (OTR) . . . . . . . . . . . . . . . . . . . . 21 Digital offset . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Output codes versus input voltage . . . . . . . . . 22 Serial Peripheral Interface (SPI) . . . . . . . . . . . 22 Register description . . . . . . . . . . . . . . . . . . . . 22 Default modes at start-up . . . . . . . . . . . . . . . . 23 Register allocation map . . . . . . . . . . . . . . . . . 25 12 13 14 14.1 14.2 14.3 14.4 15 16 Package outline. . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 32 33 33 33 33 34 34 35
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 12 April 2010 Document identifier: ADC1115S125_1

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